1. Field of the Invention
The invention relates to cache systems used in computer systems, and more particularly to a circuit to correct errors in lock cycles passed by a second level cache controller.
2. Description of the Related Art
Computer systems are getting ever more powerful. Originally personal computers used a simple 8 and 16 bit microprocessor at a relatively slow clock rate. As the capabilities of the microprocessors and subsystems improved, so did system performance. 16 and 32 bit microprocessors were used and clock rates increased from 2 or 4.77 MHZ to 66 MHZ. Memory speeds increased, though not quite at the same rate as the performance increase in the microprocessors. To partially alleviate this lag, memory system architectures became more elaborate. Cache memory systems were used to bridge the speed gap. Eventually a cache system was integrated onto the microprocessor, with second level external cache systems being used in performance oriented cases. Many computer systems using second level caches and multiple processors were produced, such as the SYSTEMPRO XL and PROLIANT.RTM. 2000 and 4000 computer systems from Compaq Computer Corporation. These particular computer systems used Intel Corporation PENTIUM.RTM. processors and the 82496/82491 chips to form the second level cache system. Because of performance limitations in those systems during four processor use, a third level cache system was added to each processor board. The third level cache was 2 Mbytes in size and reduced host or common processor bus utilization to a level to allow four processor operation without bus saturation. Details of this design are provided in U.S. patent application Ser. No. 08/237,779, filed May 4, 1994, and entitled "PROCESSOR BOARD HAVING A SECOND LEVEL WRITEBACK CACHE SYSTEM AND A THIRD LEVEL WRITETHROUGH CACHE SYSTEM WHICH STORES EXCLUSIVE STATE INFORMATION FOR USE IN A MULTIPROCESSOR COMPUTER SYSTEM", now U.S. Pat. No. 5,561,779 issued Oct. 1, 1996 which is hereby incorporated by reference. However, the requirement for a third level cache system increased the complexity and cost of the processor boards.
Intel ultimately designed next generation versions of the 82496/82491 chips, referred to as the C55 cache controller and the C88 cache RAMs. These new chips allowed the second level cache to be expanded to 2 Mbytes, from 512 kbytes for the 82496/82491, thus obviating the need for the third level cache. Therefore it was desirable to utilize these chips in a new processor board design. However, certain problems were eventually found in the C55 cache controller, which problems needed corrected to allow a processor board to operate properly. These problems are described in detail in the detailed description of the preferred embodiment.